Xilinx, has taped out its first 20nm FPGA. The chip uses a new chip architecture, which adopts Asic techniques to tackle the interconnect and clocking performance, and power issues of large FPGAs.

SAN JOSE, Calif., May 3 /PRNewswire/ — Xilinx (Nasdaq: XLNX) today introduced the ISE® Design Suite 12 software to enable breakthrough optimizations for power and cost with greater design productivity ...

Intelligent clock gating is key to Xilinx’s bid to reduce dynamic block-RAM (BRAM) power consumption in its Virtex-6 FPGA designs. The key to this fourth generation partial reconfiguration design flow ...

What is the purpose of this paper? This paper gives potential users an easy-to-grasp idea of the device functions of Xilinx Spartan-6 FPGAs. It describes the functionality of these devices in far more ...

Xilinx has unveiled its fourth generation partial reconfiguration design flow and improvements to its intelligent clock gating technology, said to reduce dynamic block ram power consumption in ...

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.

SAN JOSE, Calif., May 16, 2005 - Xilinx, Inc. (NASDAQ: XLNX) today announced immediate availability of the performance-optimized 4.00 version of its MicroBlazeâ„¢ soft processor. The 32-bit RISC core ...

Spartan-3 FPGAs Provides Customers with the Benefits of Programmability Without the Excessive Conversion or Re-qualification Costs Associated with FPGA-to-ASIC Conversions SAN JOSE, Calif., June 23, ...

PORTLAND, Ore.--(BUSINESS WIRE)--Opal Kelly, a leading producer of powerful Field Programmable Gate Array (FPGA) modules that provide essential device-to-computer interconnect, today announced the ...

Bangalore: Programmable logic solutions provider Xilinx has unveiled its architecture for next-generation FPGA products that will be built on 28 nanometer high-k metal gate at TSMC and Samsung. Using ...