EDN

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...
Semiconductor Engineering

Overview Of Security Verification Methodologies for SoC Designs Pre-Silicon (U. of Florida)

A technical paper titled “A Survey on SoC Security Verification Methods at the Pre-silicon Stage” was recently published by researchers at University of Florida. “This paper presents a survey of the ...
Semiconductor Engineering

Improving Verification Methodologies

Methodology improvements and automation are becoming pivotal for keeping pace with the growing complexity and breadth of the tasks assigned to verification teams, helping to compensate for lagging ...
Design-Reuse

Maximizing Verification Productivity: eVC Reuse Methodology (eRM)

Verification managers engaged in complex IC development projects are under constant pressure to reduce the time and cost of verification, yet they lack the necessary resources. This manuscript ...
Design-Reuse

SoC interconnect performance verification methodology based on hardware emulator

This paper describes an interconnect performance verification methodology which was developed for a complex multi source digital television SoC project. The historical and technical reasons of the ...
EDN

Formal-based methodology cuts digital design IP verification time

When we talk about the signoff of digital IP, we are referring to the full verification of a block. Every feature listed in a device’s datasheet requires verification. Furthermore, every register ...