Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...
Design-Reuse

Sequential architecture for absolutely NO hold requirement in the Shift path

Scannability has always been a challenge and with complex architectures, the challenge is exacerbated by imposing several limitations like HOLD closure, yield loss, silicon failures due to HOLD, scan ...
Design-Reuse

Dual edge sequential architecture capable of eliminating complete hold requirement from the test path

Freescale Semiconductor India Pvt. Ltd. Scannability has always been a challenge and with the complex architectures, challenges gets multifold by imposing several limitations like HOLD closure, yield ...
EDN

10 tips for successful scan design: part two

Make all clocks and asynchronous resets come from chip pins during scan mode. Ensure that all scan elements on a scan chain are in the same clock domain. Know the requirements and limitations of your ...
EDN

Scan basics

Scan technology enables high levels of defect detection using automated tools. Each D flip-flop (DFF) or latch in the circuit under test is implemented as an equivalent sequential element called a ...