EDN

IEEE Spectrum Online Article Warns Savvy System Designers of the Multicore Memory Wall

As a long-term, Senior member of the IEEE, I did feel a pang or two when I wrote up the minor technical gaffe that appeared in an IEEE Spectrum article for my previous blog entry. I’m delighted to ...
Semiconductor Engineering

UMI Can Scale the Memory Wall

While the improvements in processor performance to enable the incredible compute requirements of applications like Chat-GPT get all the headlines, a not-so-new phenomenon known as the memory wall ...
EDN

DESIGN West remembers memory

DESIGN West is under way this week in San Jose. The four-day meeting combines the Embedded Systems Conference & Exhibition with additional technical summits on a range of topics including multicore, ...
Semiconductor Engineering

UMI: Extending Chiplet Interconnect Standards To Deal With The Memory Wall

With the Open Compute Project (OCP) Summit upon us, it’s an appropriate time to talk about chiplet interconnect (in fact the 2024 OCP Summit has a whole day dedicated to the multi-die topic, on ...