Duke Pratt School of Engineering

Study Finds Next-Generation Transistor Performance Inflated in Most Lab Testing

Duke engineers show how a common device architecture used to test 2D transistors overstates their performance prospects in real-world devices.
Compound Semiconductor

Has 2D transistors' performance been inflated?

The research 'Impact of Contact Gating on Scaling of Monolayer 2D Transistors Using a Symmetric Dual-Gate Structure' appeared ...
Nanowerk

Common lab design inflates 2D transistor performance by up to six times

Lab architecture used to test 2D semiconductors artificially boosts performance metrics, making it harder to assess whether these materials can truly replace silicon.
Business Wire

GLOBALFOUNDRIES Unveils FinFET Transistor Architecture Optimized for Next-Generation Mobile Devices

MILPITAS, Calif.--(BUSINESS WIRE)--GLOBALFOUNDRIES today accelerated its leading-edge roadmap with the launch of a new technology designed for the expanding mobile market. The company’s 14nm-XM ...